MC10H180 Datasheet, PDF (1/4 Pages) ON Semiconductor – Dual 2 Bit Adder/Subtractor

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Bit Adder/Subtractor
The MC10H180 is a high–speed, low–power, general–purpose adder/
subtractor. It is designed to be used in special purpose adders/subtractors or in
high–speed multiplier arrays.
Inputs for each adder are Carry–in, Operand A, and Operand B; outputs are
Sum, Sum and Carry–out. The common select inputs serve as a control line to
Invert A for subtract, and a control line to Invert B.
• Propagation Delay, 1.8 ns Typical, Operand and Select to Output
• Power Dissipation, 360 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MC10H180
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
IE
Input Current High
IinH
Pins 4, 12
Pins 7, 9
Pins 5, 6, 10, 11
— 95 — 86 —
— 665 — 417 —
— 515 — 320 —
— 410 — 255 —
95 mA
µA
417
320
255
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage (1)
Low Input Voltage (1)
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5 —
0.5 —
0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
Operand to Output
Select to Output
Carry–in to Output
tpd
ns
0.6 2.4 0.7 2.5 0.8 2.8
0.6 2.2 0.7 2.3 0.8 2.6
0.4 1.6 0.4 1.7 0.4 1.8
Rise Time
tr
0.5 2.0 0.5 2.1 0.5 2.2 ns
Fall Time
tf
0.5 2.0 0.5 2.1 0.5 2.2 ns
NOTES:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
7
SELA S0
15
9
SELB ^S0
2
5
AO
6
BO
4
CIN COUT
3
SELA S1
14
SELB ^S1
1
11
A1
10
B1
12
CIN COUT
13
VCC = PIN 16
VEE = PIN 8
POSITIVE LOGIC ONLY
  A’ = A SELA = A SELA
  B’ = B SELB = B SELB
S = CIN (A’ B’ + A’ B’) +
CIN(A’ B’ + A’ B’)
COUT = CINA’ + CINB’ + A’ B’
DIP
PIN ASSIGNMENT
S1
1
16
VCC
S0
2
15 S0
COUT
3
14 S1
CIN
4
A0
5
B0
6
13
COUT
12 CIN
11 A1
SELA
7
VEE
8
10 B1
9
SELB
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–271
REV 5