MC10H171 Datasheet, PDF (1/4 Pages) ON Semiconductor – Dual Binary to 1-4 Decoder (Low)

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Binary to 1-4 Decoder
(Low)
The MC10H171 is a binary coded 2 line to dual 4 line decoder with selected
outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are
high. The common enable E, when high, forces all outputs high.
• Propagation Delay, 2 ns Typical
• Power Dissipation 325 mW Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K–Compatible
MC10H171
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
Input Current High
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IE
IinH
IinL
VOH
VOL
VIH
VIL
— 85 — 77 —
85 mA
— 425 — 265 — 265 µA
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Characteristic
0°
25°
75°
Symbol Min Max Min Max Min Max Unit
Propagation Delay
Data
Select
tpd
ns
0.5 2.0 0.5 2.1 0.5 2.2
0.5 2.6 0.5 2.7 0.5 2.8
Rise Time
tr
0.5 1.7 0.5 1.8 0.5 1.9 ns
Fall Time
tf
0.5 1.7 0.5 1.8 0.5 1.9 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
E0 14
A9
B7
E 15
E1 2
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
10 Q0 3
11 Q0 2
12 Q0 1
13 Q0 0
3 Q1 3
4 Q1 2
5 Q1 1
6 Q1 0
DIP
PIN ASSIGNMENT
VCC1
1
E1
2
Q13
3
Q12
4
Q11
5
Q10
6
B
7
VEE
8
16
VCC2
15
E
14
E0
13
Q00
12
Q01
11
Q02
10
Q03
9
A
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–9
REV 5