MC10H160 Datasheet, PDF (1/3 Pages) ON Semiconductor – 12-Bit Parity Generator-Checker

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
12-Bit Parity
Generator-Checker
MC10H160
The MC10H160 is a 12–bit parity generator–checker. The output goes high
when an odd number of inputs are high providing the odd parity function.
Unconnected inputs are pulled to a logic low allowing parity detection and
generation for less than 12 bits. The MC10H160 is a functional pin duplication
of the standard 10K family part with 100% improvement in propagation delay
and no increase in power–supply current.
• Propagation Delay, 2.5 ns Typical
• Power Dissipation, 320 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
IE
Input Current High
IinH
Pins 3,5,7,10,12,14
Pins 4,6,9,11,13,15
— 88 — 78 —
— 391 — 246 —
— 457 — 285 —
88 mA
µA
246
285
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
tpd
1.1 3.1 1.1 3.3 1.2 3.5 ns
Rise Time
tr
0.55 1.5 0.55 1.6 0.75 1.7 ns
Fall Time
tf
0.55 1.5 0.55 1.6 0.75 1.7 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
3
VCC1 = PIN 1
4
VCC2 = PIN 16
5
VEE = PIN 8
6
7
9
2
10
11
12
13
14
15
TRUTH TABLE
INPUT
Sum of
High Level
Inputs
OUTPUT
Pin 2
Even
Odd
Low
High
DIP
PIN ASSIGNMENT
VCC1
1
OUT
2
IN1
3
IN2
4
IN3
5
IN4
6
IN5
7
VEE
8
16
VCC2
15
IN12
14
IN11
13
IN10
12
IN9
11
IN8
10
IN7
9
IN6
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–246
REV 5