MC10H016 Datasheet, PDF (1/4 Pages) ON Semiconductor – 4-Bit Binary Counter

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Binary Counter
The MC10H016 is a high–speed synchronous, presettable, cascadable
4–bit binary counter. It is useful for a large number of conversion, counting and
digital integration applications.
• Counting Frequency, 200 MHz Minimum
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
• Positive Edge Triggered
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
–8.0 to 0
Vdc
VI
0 to VEE
Vdc
Iout
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
Input Current High
All Except MR
Pin 12 MR
IE
—
126
—
115
—
126 mA
IinH
µA
—
450
—
265
—
265
— 1190 —
700
—
700
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5
—
0.5
—
0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
Clock to Q
Clock to TC
MR to Q
tpd
ns
1.0
2.4
1.0
2.5
1.0
2.7
0.7
2.4
0.7
2.5
0.7
2.6
0.7
2.4
0.7
2.5
0.7
2.6
Set–up Time
Pn to Clock
CE or PE to Clock
tset
ns
2.0
—
2.0
—
2.0
—
2.5
—
2.5
—
2.5
—
Hold Time
Clock to Pn
Clock to CE or PE
thold
ns
1.0
—
1.0
—
1.0
—
0.5
—
0.5
—
0.5
—
Counting Frequency
fcount
200
—
200
—
200
—
MHz
Rise Time
tr
0.5
2.0
0.5
2.1
0.5
2.2
ns
Fall Time
tf
0.5
2.0
0.5
2.1
0.5
2.2
ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
MC10H016
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
VCC1
1
Q1
2
Q0
3
TC
4
PE
5
CE
6
PO
7
VEE
8
16
VCC2
15
Q2
14
Q3
13
CP
12
MR
11
P3
10
P2
9
P1
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
TRUTH TABLE
CE PE MR CP
Function
LL
HL
LH
HH
XX
XX
L Z Load Parallel (Pn to Qn)
L Z Load Parallel (Pn to Qn)
L Z Count
L Z Hold
L ZZ Masters Respond;
Slaves Hold
H X Reset (Qn = LOW,
TC = HIGH)
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)
Features include assertion inputs and outputs on each
of the four master/slave counting flip–flops. Terminal
count is generated internally in a manner that allows
synchronous loading at nearly the speed of the basic
counter.
9/96
© Motorola, Inc. 1996
2–1
REV 6