MC10134 Datasheet, PDF (1/5 Pages) Motorola, Inc – DUAL MULTIPLEXER WITH LATCH

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Multiplexer With Latch
The MC10134 is a dual multiplexer with clocked D type latches. Each latch
may be clocked separately by holding the common clock in the low state, and
using the clock enable inputs for the clocking function. If the common clock is to
be used to clock the latch, the clock enable (CE) inputs must be in the low state.
In this mode, the enable inputs perform the function of controlling the common
clock (CC).
The data select inputs determine which data input is enabled. A high (H)
level on the A0 input enables data input D12 and a low (L) level on the A0 input
enables data input D11. A high (H) level on the A1 input enables data input D22
and a low (L) level on the A1 input enables data input D21.
Any change on the data input will be reflected at the outputs while the clock is
low. The outputs are latched on the positive transition of the clock. While the
clock is in the high state, a change in the information present at the data inputs
will not affect the output information.
PD = 225 mW typ/pkg (No Load)
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)
A0 6
A1 11
D11 4
LOGIC DIAGRAM
D12 5
CEO 10
CC 7
CE1 9
D21 13
D22 12
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
C A0 D11 D12 Qn+1
LLLX
L
L LHX
H
L HX L
L
LHXH
H
HXXX
Qn
C = CE + CC
2 Q1
3 Q1
15 Q2
14 Q2
MC10134
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
VCC1
1
Q1
2
Q1
3
D11
4
D12
5
A0
6
CC
7
VEE
8
16
VCC2
15
Q2
14
Q2
13
D21
12
D22
11
A1
10
CEO
9
CE1
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–17
REV 5