MC10133 Datasheet, PDF (1/4 Pages) Motorola, Inc – Quad Latch

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Latch
The MC10133 is a high speed, low power, quad latch consisting of four
bistable latch circuits with D type inputs and gated Q outputs, allowing direct
wiring to a bus. When the clock is high, outputs will follow D inputs. Information
is latched on the negative going transition of the clock.
The outputs are gated when the output enable (G) is low. All four latches may
be clocked at one time with the common clock (CC), or each half may be
clocked separately with its clock enable (CE).
PD = 310 mW typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
D0 3
LOGIC DIAGRAM
Q0
2 Q0
G0 5
D1 7
CE 4
CC 13
CE 12
D2 9
G1 10
6 Q1
Q1
Q2
11 Q2
D3 14
Q3
TRUTH TABLE
GCD
HXX
LLX
LHL
L HH
C = CC + CE
Qn+1
L
Qn
L
H
15 Q3
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
MC10133
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
DIP
PIN ASSIGNMENT
VCC1
1
Q0
2
D0
3
CE
4
G0
5
Q1
6
D1
7
VEE
8
16
VCC2
15
Q3
14
D3
13
CC
12
CE
11
Q2
10
G1
9
D2
9/96
© Motorola, Inc. 1996
3–13
REV 6