MC10111 Datasheet, PDF (1/4 Pages) ON Semiconductor – Dual 3−Input/3−Ouput NOR Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 3-Input/3-Output NOR
Gate
The MC10111 is designed to drive up to three transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines from a single point makes the
MC10111 particularly useful in clock distribution applications where minimum
clock skew is desired. Three VCC pins are provided and each one should be
used.
PD = 80 mW typ/gate (No Load)
tpd = 2.4 ns typ (All Outputs Loaded)
tr, tf = 2.2 ns typ (20%–80%)
MC10111
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
LOGIC DIAGRAM
2
5
3
6
4
7
12
9
13
10
14
11
VCC1 = PIN 1,15
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
AOUT
4
AIN
5
AIN
6
AIN
7
VEE
8
16
VCC2
15
VCC1
14
BOUT
13
BOUT
12
BOUT
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
© Motorola, Inc. 1996
3–44
REV 6