MC100LVEL37 Datasheet, PDF (1/3 Pages) ON Semiconductor – 1:4 ÷1/÷2 ECL/PECL Clock Fanout Buffer

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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÷ ÷ 1:4 1/ 2 ECL/PECL Clock
Fanout Buffer
The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device
offers two outputs at ÷1 of the input frequrency, and two outputs at ÷2 of
the input frequency. The Low Output–Output Skew of the device makes it
ideal for distributing1x and 1/2x frequency synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are left
open the D input will pull down to VEE, The D input will bias around VCC/2
and the Q output will go LOW.
• Differential Inputs and Outputs
• 20–Lead SOIC Packaging
• 700ps Typical Propagation Delays
• 50ps Output–Output Skews
• Low Voltage 100K ECL
• >2000V ESD Protection
NC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 NC
20 19 18 17 16 15 14 13 12 11
÷1 ÷2
1 2 3 4 5 6 7 8 9 10
NC VCC CLK0 CLK0 Clk_Sel CLK1 CLK1 MR VEE NC
Figure 1. 20–Lead Pinout (Top View)
MC100LVEL37
DW SUFFIX
20–LEAD PLASTIC SOIC WIDE PACKAGE
CASE 751D–04
PIN NAMES
Pins
Function
Qna, Qna
CLKn, CLKn
Clk_Sel
MR
Differential Clock Outputs
Differential Clock Inputs
Input Clock Selection
‘0’ Selects CLK0; ‘1‘ Selects CLK1
Asynchronous Master Reset
‘1’ Resets Dividers
MC100LVEL37
DC CHARACTERISTICS (VEE = –3.0V to –3.8V; VCC = GND)
–40°C
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
IEE
Power Supply Current
38
38
38
38
mA
IIH
Input HIGH Current
150
150
150
150 µA
IINL
Input LOW Current CLKn 0.5
0.5
0.5
0.5
µA
CLKn –300
–300
–300
–300
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
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© Motorola, Inc. 1997
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