MC100LVE210 Datasheet, PDF (1/6 Pages) ON Semiconductor – Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage Dual 1:4, 1:5
Differential Fanout Buffer
ECL/PECL Compatible
MC100LVE210
MC100E210
The MC100LVE210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device features
two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device
features fully differential clock paths to minimize both device and system
skew. The dual buffer allows for the fanout of two signals through a single
chip, thus reducing the skew between the two fundamental signals from a
part–to–part skew down to an output–to–output skew. This capability
reduces the skew by a factor of 4 as compared to using two LVE111’s to
accomplish the same task. The MC100LVE210 works from a –3.3V
supply while the MC100E210 provides identical function and
performance from a standard –4.5V 100E voltage supply.
LOW VOLTAGE
DUAL 1:4, 1:5 DIFFERENTIAL
FANOUT BUFFER
• Dual Differential Fanout Buffers
• 200ps Part–to–Part Skew
• 50ps Typical Output–to–Output Skew
• Low Voltage ECL/PECL Compatible
• 28–lead PLCC Packaging
For applications which require a single–ended input, the VBB reference
voltage is supplied. For single–ended input applications the VBB
reference should be connected to the CLK input and bypassed to ground
via a 0.01µf capacitor. The input signal is then driven into the CLK input.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50Ω, even if only
one side is being used. In most applications all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used it is necessary to terminate at least the output pairs
adjacent to the output pair being used in order to maintain minimum skew.
Failure to follow this guideline will result in small degradations of
propagation delay (on the order of 10–20ps) of the outputs being used,
while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another
such that the guideline expressed above holds only for outputs on the
same side of the package.
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
The MC100LVE210, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVE210 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE210’s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note
AN1406/D.
7/95
© Motorola, Inc. 1996
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