MC100LVE111 Datasheet, PDF (1/5 Pages) Motorola, Inc – LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
LowĆVoltage 1:9 Differential
ECL/PECL Clock Driver
MC100LVE111
The MC100LVE111 is a low skew 1-to-9 differential driver, designed
with clock distribution in mind. The MC100LVE111’s function and
performance are similar to the popular MC100E111, with the added
feature of low voltage operation. It accepts one signal input, which can be
either differential or single-ended if the VBB output is used. The signal is
fanned out to 9 identical differential outputs.
• 200ps Part-to-Part Skew
• 50ps Output-to-Output Skew
• Differential Design
• VBB Output
• Voltage and Temperature Compensated Outputs
• Low Voltage VEE Range of –3.0 to –3.8V
• 75kΩ Input Pulldown Resistors
LOW-VOLTAGE
1:9 DIFFERENTIAL
ECL/PECL CLOCK DRIVER
The LVE111 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate to
gate skew within a device, and empirical modeling is used to
determineprocess control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50Ω, even if only
one side is being used. In most applications, all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used, it is necessary to terminate at least the output pairs on the
same package side as the pair(s) being used on that side, in order to
maintain minimum skew. Failure to do this will result in small degradations
of propagation delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs, will mean a
loss of skew margin.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
The MC100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the LVE111 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111’s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination
offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage. For more information on using PECL,
designers should refer to Motorola Application Note AN1406/D.
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© Motorola, Inc. 1996
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