MC100ES6130 Datasheet, PDF (1/8 Pages) Motorola, Inc – 2.5/3.3V 1:4 PECL Clock Driver with 2:1 Input MUX

Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MC100ES6130
Rev 1, 5/2004
2.5/3.3V 1:4 PECL Clock Driver
with 2:1 Input MUX
The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The
ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a
2:1 input MUX which is ideal for redundant clock switchover applications. This
device also includes a synchronous enable pin that forces the outputs into a
fixed logic state. Enable or disable state is initiated only after the outputs are
in a LOW state to eliminate the possibility of a runt clock pulse.
Features
• 2 GHz maximum output frequency
• 25 ps maximum output-to-output skew
• 150 ps part-to-part skew
• 350 ps typical propagation delay
• 2:1 differential MUX input
• 2.5 / 3.3 V operating range
• LVPECL and HSTL input compatible
• 16-lead TSSOP package
• Temperature range –40°C to +85°C
MC100ES6130
DT SUFFIX
16 LEAD TSSOP PACKAGE
CASE 948F
ORDERING INFORMATION
Device
MC100ES6130DT
MC100ES6130DTR2
Package
TSSOP-16
TSSOP-16
Q0 1
Q0 ₂
Q1 3
Q1 4
Q2 5
Q2 ₆
Q3 7
Q3 8
QD
16 ^VCC
15 ^EN
14 IN1
13 IN1
12 IN0
11 ^IN0
10 IN_SEL
9 V_EE
Figure 1. 16-Lead Pinout (Top View) and Logic Diagram
© Motorola, Inc. 2004
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