DSP96002 Datasheet, PDF (1/111 Pages) Motorola, Inc – 32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR

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SEMICONDUCTOR TECHNICAL DATA
DSP96002/D, Rev. 2
DSP96002
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT
PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units
operating in parallel. The DSP96002 has two identical memory expansion ports with control
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which
facilitates easy interface with other processors for multiprocessor applications. Linear arrays
of DSP96002s can be implemented without glue logic. The MPU-style programming model
and instruction set allow straightforward generation of efficient, compact code. The high
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive
applications that require floating-point processing and access to large memory subsystems.
Control _Bus
18 ^Control
Address
32 ^External
Address
Switch
4
32-bit
Host
Interface
Timer
32
Data
External
Data
Bus
Switch
Address
Generation
Unit (AGU)
Dual Channel
DMA
Controller
Internal
Switch And Bit
Manipulation
Unit
YAB*
XAB*
PAB*
Program _*
Memory
1024 × 32
RAM and
64 × 32
Bootstrap
ROM
Instruction
Cache
X Data ^*
Memory
512 × 32
RAM
512 × 32†
ROM
Y Data ^*
Memory
512 × 32
RAM
512 × 32†
ROM
DDB
YDB
XDB
PDB
GDB
Bus ^Control
Control ₁₈
External
Address
Address
32
Switch
4
32-bit
Host
Interface
Timer
External
Data
Bus
Switch
32
Data
Clock
Generator
Program
Decode
Controller
Program
Address
Generator
Program
Interrupt
Controller
Program Controller
Data ALU
OnCE
Debug
• IEEE Floating Point _Controller
• 32 × 32 Integer ALU
CLK
32-bit Buses
* ^{Dual Access (DMA/Core)}
† _{1024 × 32 Virtual Locations}
MODC/IRQC
MODB/IRQB
MODA/IRQA
RESET
4
Serial Debug
Port
AA0306
Figure 1 Block Diagram
©1996 MOTOROLA, INC.
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