AN535 Datasheet, PDF (1/12 Pages) Motorola, Inc – PHASE LOCKED LOOP DESIGN FUNDAMENTALS

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR APPLICATION NOTE
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AN535
PhaseĆLocked Loop Design Fundamentals
Prepared by: Garth Nash
Applications Engineering
ABSTRACT
The fundamental design concepts for phase-locked loops
implemented with integrated circuits are outlined. The
necessary equations required to evaluate the basic loop
performance are given in conjunction with a brief design
example.
INTRODUCTION
The purpose of this application note is to provide the
electronic system designer with the necessary tools to design
and evaluate Phase-Locked Loops (PLL) configured with
integrated circuits. The majority of all PLL design problems
can be approached using the Laplace Transform technique.
Therefore, a brief review of Laplace is included to establish a
common reference with the reader. Since the scope of this
article is practical in nature all theoretical derivations have
been omitted, hoping to simplify and clarify the content. A
bibliography is included for those who desire to pursue the
theoretical aspect.
PARAMETER DEFINITION
The Laplace Transform permits the representation of the
time response f(t) of a system in the complex domain F(s).
This response is twofold in nature in that it contains both
transient and steady state solutions. Thus, all operating
conditions are considered and evaluated. The Laplace
transform is valid only for positive real time linear parameters;
thus, its use must be justified for the PLL which includes both
linear and nonlinear functions. This justification is presented
in Chapter Three of Phase Lock Techniques by Gardner.¹
The parameters in Figure 1 are defined and will be used
throughout the text.
+
θ_e(s)
θ_i(s)
G(s)
–
θ_o(s)
H(s)
θ_i(s) Phase Input
θ_e(s) Phase Error
θ_o(s) Output Phase
G(s) Product of the Individual Feed
Forward Transfer Functions
H(s) Product of the Individual Feedback
Transfer Functions
Figure 1. Feedback System
Using servo theory, the following relationships can be
obtained.²
q_e(s)
+
1
)
1
G(s)
H(s)
q_i(s)
(1)
q_o(s)
+
1
)
G(s)
G(s)
H(s)
q_i(s)
(2)
These parameters relate to the functions of a PLL as shown
in Figure 2.
θ_i(s)
f_i
Phase Detector
θ_e(s)
fo _θo(s)/N
N
Filter
Programmable
Counter (÷N)
θ_o(s)
VCO/VCM
f_o
Figure 2. Phase Locked Loop
REV 0
© Motorola, Inc. 1994
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