AN211A Datasheet, PDF (1/12 Pages) Motorola, Inc – FIFELD EFFECT TRANSISTORS IN THEORY AND PRACTICE

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR APPLICATION NOTE
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by AN211A/D
NOTE: The theory in this application note is still applicable,
but some of the products referenced may be discontinued.
Field Effect Transistors in Theory
and Practice
AN211A
INTRODUCTION
There are two types of field-effect transistors, the Junction
Field-Effect Transistor (JFET) and the “Metal-Oxide
Semiconductor” Field-Effect Transistor (MOSFET), or
Insulated-Gate Field-Effect Transistor (IGFET). The
principles on which these devices operate (current controlled
by an electric field) are very similar — the primary difference
being in the methods by which the control element is made.
This difference, however, results in a considerable difference
in device characteristics and necessitates variances in circuit
design, which are discussed in this note.
DRAIN
DRAIN
GATE
GATE
SOURCE
SOURCE
NĆCHANNEL JFET
PĆCHANNEL JFET
JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
In its simplest form the junction field-effect transistor starts
with nothing more than a bar of doped silicon that behaves
as a resistor (Figure 1a). By convention, the terminal into
which current is injected is called the source terminal, since,
as far as the FET is concerned, current originates from this
terminal. The other terminal is called the drain terminal.
Current flow between source and drain is related to the
drain-source voltage by the resistance of the intervening
material. In Figure 1b, p-type regions have been diffused into
the n-type substrate of Figure 1a leaving an n-type channel
between the source and drain. (A complementary p-type
device is made by reversing all of the material types.) These
p-type regions will be used to control the current flow
between the source and the drain and are thus called gate
regions.
As with any p-n junction, a depletion region surrounds
the p-n junctions when the junctions are reverse biased
(Figure 1c). As the reverse voltage is increased, the
depletion regions spread into the channel until they meet,
creating an almost infinite resistance between the source and
the drain.
If an external voltage is applied between source and drain
(Figure 1d) with zero gate voltage, drain current flow in the
channel sets up a reverse bias along the surface of the gate,
parallel to the channel. As the drain-source voltage
increases, the depletion regions again spread into the
channel because of the voltage drop in the channel which
reverse biases the junctions. As V_DS is increased, the
depletion regions grow until they meet, whereby any further
increase in voltage is counterbalanced by an increase in the
depletion region toward the drain. There is an effective
increase in channel resistance that prevents any further
increase in drain current. The drain-source voltage that
causes this current limiting condition is called the “pinchoff”
voltage (V_p). A further increase in drain-source voltage
produces only a slight increase in drain current.
The variation in drain current (I_D) with drain-source
voltage (V_DS) at zero gate-source voltage (V_GS) is shown
in Figure 2a. In the low-current region, the drain current is
linearly related to V_DS. As I_D increases, the “channel” begins
to deplete and the slope of the I_D curve decreases. When
the V_DS is equal to V_p, I_D “saturates” and stays relatively
constant until drain-to-gate avalanche, V_BR(DSS) is reached.
If a reverse voltage is applied to the gates, channel pinch-off
occurs at a lower I_D level (Figure 2b) because the depletion
region spread caused by the reverse-biased gates adds to
that produced by V_DS. Thus reducing the maximum current
for any value of V_DS.
È ÈÈ SOURCE
N
DRAIN
ÈÈ ÈÈÈÈ _{ÈÇÇÈ (a)}
ÈÈÇÇÇÇÈÈ _{GATE 1}
SOURCE
GATE 1
P
N
P
DRAIN
ÈÈÈÇÇÇÇÇÇÈÈÈÇÇÇ _SOURCE
(-) _{DEPLETION ZONES}
P
N
DRAIN
P
GATE 2
(b)
(-) GATE 2
(c)
ÈÈÈÇÇÇÈÈÈÇÇÇÇÇÇÈÈÈ _SOURCE
GATE 1
P
(+)
I_D
P
DRAIN
+V_DS
I_D
GATE 2
(d)
Figure 1. Development of Junction
Field-Effect Transistors
V_P LOCUS
I_D
V_GS = 0
I_P
I_D
V_GS = 0
V_GS = - 1 V
V_GS = - 2 V
V_P
V_(BR)DSS
V_DS
V_DS
(a)
(b)
Figure 2. Drain Current Characteristics
REV 0
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