56F827 Datasheet, PDF (1/52 Pages) Motorola, Inc – 56F827 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
DSP56F827/D
Rev. 9.0, 02/2004
56F827
Technical Data
56F827 16-bit Hybrid Controller
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• 64K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 4K × 16-bit words Data Flash
• 4K × 16-bit words Data RAM
• Up to 64K × 16-bit words external memory
expansion each for Program and Data memory
• JTAG/OnCE™ for debugging
• General Purpose Quad Timer
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• 8-channel Programmable Chip Select
• 10-channel, 12-bit ADC
• Synchronous Serial Interface (SSI)
• Serial Port Interface (SPI)
• Serial Communications Interface (SCI)
• Time-of-Day (TOD) Timer
• 128-pin LQFP Package
• 16-dedicated and 48 shared GPIO
EXTBOOT _DEBUG
inputs
10
V_REFP, V_REFMID,
V_REFIN
3
V_REFLO
V_REFHI
ADC
RESET
IRQB
IRQA
6
JTAG/
OnCE
Port
V_DDIO V_SSIO V_DD V_SS V_DDA V_SSA
5
5
3
4
2
2
Low Voltage Supervisor Analog Reg
Interrupt
Controller
Program Controller
and Hardware
Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
4
VPP
2
6
4
4
PCS [2:7}
6
Quad Timer A/
or GPIO
SCI 2 or
GPIO
SSI 0 or
GPI0
SCI 0 &1 or
SPI 0
SPI 1 or
GPIO
Programmable
Chip Select
Program and Boot
Memory
64512 x 16 Flash
1024 x 16 SRAM
Data Memory
4096 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
Application-
Specific
Memory &
Peripherals
PAB
PDB
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
16
COP
RESET
IPBB
CONTROLS
16
MODULE
CONTROLS
ADDRESS
BUS [8:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock
Gen
External
Address Bus
External
Bus
Switch
16
Interface
Unit
External
Data Bus
Switch
16
Dedicated
16
GPIO
TOD
Timer
DATA
BUS [15:0]
Bus
Control
CLKO
XTAL
EXTAL
A[00:15]
or
GPIOA16[00:16]
D[00:15]
or
GPIOG16[00:16]
PS or PCS[0]
DS or PCS[1]
WR
RD
Figure 1. 56F827 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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