V827464N24S Datasheet, PDF (9/15 Pages) Mosel Vitelic, Corp – 2.5 VOLT 64M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE

MOSEL VITELIC
V827464N24S
DDR SDRAM I_DD SPEC TABLE
Symbol
A1
B0
B1
C0
PC1600@CL2 PC2100B@CL2.5 PC2100A@CL2 PC2700@CL2.5
Unit
IDD6
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
Normal
Low power
IDD7
1640
1860
280
640
640
280
1100
2700
2360
3260
54
33
4600
1860
2180
380
640
740
380
1280
3440
3080
3440
54
33
5400
1860
2180
380
640
740
380
1280
3440
3080
3440
54
33
5400
1990
mA
2540
mA
460
mA
280
mA
190
mA
370
mA
550
mA
1700
mA
1600
mA
1800
mA
30
mA
33
mA
6400
mA
* Module I_DD was calculated on the basis of component I_DD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V827464N24S Rev. 1.0 August 2002
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