V54C3128804VAT Datasheet, PDF (9/43 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8

MOSEL VITELIC
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.
Bank Selection by Address Bits:
A10 BA0 BA1
000
001
010
011
1XX
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
V54C3128804VAT
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
Recommended Operation and Characteristics for LV-TTL
T_A = 0 to 70 °C; V_SS = 0 V; V_CC,V_CCQ = 3.3 V ± 0.3 V
Limit Values
Parameter
Symbol
min.
max. Unit Notes
Input high voltage
V_IH
2.0
Vcc+0.3
V
1, 2
Input low voltage
V_IL
– 0.3
0.8
V
1, 2
Output high voltage (I_OUT = –4.0 mA)
V_OH
2.4
–
V
Output low voltage (I_OUT = 4.0 mA)
V_OL
–
0.4
V
Input leakage current, any input
(0 V < V_IN < 3.6 V, all other inputs = 0 V)
I_I(L)
–5
5
µA
Output leakage current
(DQ is disabled, 0 V < V_OUT < V_CC)
I_O(L)
–5
5
µA
Note:
1. All voltages are referenced to V_SS.
2. V_IH may overshoot to V_CC + 2.0 V for pulse width of < 4ns with 3.3V. V_IL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
V54C3128804VAT Rev. 1.4 November 2000
9