V82658J04S Datasheet, PDF (8/13 Pages) Mosel Vitelic, Corp – 2.5 VOLT 8M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE

MOSEL VITELIC
DDR SDRAM module I_DD spec table
B1(DDR266@CL=2)
Symbol
typical
worst
IDD0
360
380
IDD1
560
620
IDD2P
84
100
IDD2F
160
180
IDD2Q
120
140
IDD3P
100
120
IDD3N
180
200
IDD4R
840
980
IDD4W
600
660
IDD5
780
840
IDD6
Normal
8
8
Low power
4
4
IDD7
1200
1360
B0(DDR266@CL=2.5)
typical
worst
360
380
560
620
84
100
160
180
120
140
100
120
180
200
840
980
600
660
780
840
8
8
4
4
1200
1360
V82658J04S
A1(DDR200@CL=2)
typical
worst
1280
1360
2160
2400
320
384
560
640
432
512
320
400
560
640
2480
2800
1760
2000
2880
3040
32
32
16
16
4400
4800
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
AC Characteristics (AC operating conditions unless otherwise noted)
(PC266A)
Parameter
Symbol Min Max
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Last Data-In to Read Command
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time CAS Latency = 2.5
CAS Latency = 2
t_RC
t_RFC
t_RAS
t_RCD
t_RRD
t_CCD
t_RP
t_WR
t_DRL
t_DAL
t_CK
60
-
67
-
45
120K
18
-
14
-
1
-
18
-
15
-
1
-
35
-
7
12
7.5
12
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
t_CH
t_CL
t_AC
t_DQSCK
0.45
0.45
-0.75
-0.75
0.55
0.55
0.75
0.75
(PC266B)
Min Max
65
-
75
-
48 120K
20
-
15
-
1
-
20
-
15
-
1
-
35
-
7.5
12
10
12
0.45 0.55
0.45 0.55
-0.75 0.75
-0.75 0.75
(PC200)
Min Max Unit Note
70
-
ns
80
-
ns
50 120K ns
20
-
ns
15
-
ns
1
- CLK
20
-
ns
15
-
ns
1
- CLK
35
-
ns
8
12 ns
10
12 ns
0.45 0.55 CLK
0.45 0.55 CLK
-0.8 0.8 ns
-0.8 0.8 ns
V82658J04S Rev. 1.3 March 2002
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