V436616Y24VATG-75PC Datasheet, PDF (8/12 Pages) Mosel Vitelic, Corp – 3.3 VOLT 16M x 64 HIGH PERFORMANCE 133 MHZ SDRAM UNBUFFERED SODIMM

MOSEL VITELIC
V436616Y24VATG-75PC
AC Characteristics
T_A = 0° to 70°C; V_SS = 0V; V_CC = 3.3V ± 0.3V, t_T = 1 ns (Continued)
Limit Values
-75
#
Symbol Parameter
Min.
Max.
Read Cycle
21
t_OH
22
t_LZ
23
t_HZ
24
t_DQZ
Write Cycle
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
2.7
–
1
–
–
5.4
–
2
25
t_WR
Write Recovery Time
26
t_DQW
DQM Write Mask Latency
2
–
0
–
Unit
Note
ns
2
ns
ns
7
CLK
CLK
CLK
Notes:
1. The specified values are valid when addresses are changed no more than once during t_CK(min.) and when No
Operation commands are registered on every rising clock edge during t_RC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t_RC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V_IL = 0.4V and V_IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between V_IH and V_IL. All AC measurements assume t_T = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
CLOCK
tCL
tSETUP tHOLD
INPUT
1.4V
tCH
2.4V
0.4V
t_T
+ 1.4 V
50 Ohm
Z=50 Ohm
I/O
50 pF
OUTPUT
tAC
tLZ
tAC
tOH
tHZ
1.4V
I/O
50 pF
Measurement conditions for
tac and toh
V436616Y24VATG-75PC Rev. 1.0 October 2001
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