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| V62C2802048L Datasheet, PDF (6/10 Pages) Mosel Vitelic, Corp – Ultra Low Power 256K x 8 CMOS SRAM | |||
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V62C2802048L(L)
Timing Waveform of Read Cycle 1(Address Controlled) (3,6,7,9)
tRC
Address
DOUT
tAA
tOH
Data Valid
Timing Waveform of Read Cycle 2(CE1 Controlled)(5,6,8,9)
tRC
CE1
OE
tOE
DOUT
tOLZ
tACE
tOHZ
tCHZ
Data Valid
tCLZ
tPD
Supply Current
tPU
ICC
50%
50%
ISB
Timing Waveform of Read Cycle 3(CE2 Controlled) (3,6,8,9)
tRC
CE2
OE
tOE
DOUT
tOLZ
tACE
tOHZ
tCHZ
Data Valid
tCLZ
tPD
Supply Current
tPU
ICC
50%
50%
ISB
6
REV. 1.2 May 2001 V62C2802048L(L)
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