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V53C8128H Datasheet, PDF (6/20 Pages) Mosel Vitelic, Corp – ULTRA-HIGH PERFORMANCE, 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM
MOSEL-VITELIC
AC Characteristics (continued)
JEDEC
# Symbol Symbol Parameter
27 tWL1CL2
28 tCL1WH1
29 tWL1WH1
30 tRL1WH1
tWCS
tWCH
tWP
tWCR
31 tWL1RH1 tRWL
32 tDVWL2
33 tWL1DX
34 tWL1GL2
35 tGH2DX
36 tRL2RL2
(RMW)
37 tRL1RH1
(RMW)
38 tCL1WL2
39 tRL1WL2
tDS
tDH
tWOH
tOED
tRWC
tRRW
tCWD
tRWD
40 tCL1CH1
41 tAVWL2
42 tCL2CL2
tCRW
tAWD
tPC
43 tCH2CL2
44 tAVRH1
tCP
tCAR
45 tCH2QV
tCAP
46 tRL1DX
tDHR
47 tCL1RL2 tCSR
48 tRH2CL2
49 tRL1CH1
tRPC
tCHR
50 tCL2CL2
(RMW)
tPCM
Write Command Setup Time
Write Command Hold Time
Write Pulse Width
Write Command Hold Time
from RAS
Write Command to RAS
Lead Time
Data in Setup Time
Data in Hold Time
Write to OE Hold Time
OE to Data Delay Time
Read-Modify-Write
Cycle Time
Read-Modify-Write Cycle
RAS Pulse Width
CAS to WE Delay
RAS to WE Delay in
Read-Modify-Write Cycle
CAS Pulse Width (RMW)
Col. Address to WE Delay
EDO Page Mode
Read or Write Cycle Time
CAS Precharge Time
Column Address to RAS
Setup Time
Access Time from
Column Precharge
Data in Hold Time
Referenced to RAS
CAS Setup Time
CAS-before-RAS Refresh
RAS to CAS Precharge Time
CAS Hold Time
CAS-before-RAS Refresh
EDO Page Mode Read-
Modify-Write Cycle Time
V53C8128H
35
40
45
50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Notes
0
0
0
0
ns 12, 13
5
5
6
7
ns
5
5
6
7
ns
28
30
35
40
ns
12
12
13
14
ns
0
0
0
0
4
5
6
7
5
6
7
8
5
6
7
8
105
110
115
130
ns
14
ns
14
ns
14
ns
14
ns
70
75
80
87
ns
28
30
32
34
54
58
62
68
ns
12
ns
12
46
48
50
52
35
38
41
42
14
15
17
19
ns
ns
12
ns
4
5
6
7
ns
18
20
22
24
ns
21
23
25
27 ns
7
28
30
35
40
ns
10
10
10
10
ns
0
0
0
0
ns
8
8
10
12
ns
58
60
65
70
ns
V53C8128H Rev. 1.1 November 1997
6