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V53C1664H Datasheet, PDF (6/18 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 64K X 16 BIT FAST PAGE MODE DUAL CAS CMOS DYNAMIC RAM
MOSEL VITELIC
V53C1664H
AC Characteristics (Cont’d)
30
35
40
45
50
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
tWP
Write Pulse Width
5
5
5
6
7
ns
tWCR
Write Command Hold Time
26
28
30
35
40
ns
from RAS
tRWL
Write Command to RAS
Lead Time
10
11
12
13
14
ns
tDS
Data in Setup Time
0
0
0
0
0
ns 14
tDH
Data in Hold Time
5
5
5
6
7
ns 14
tWOH
Write to OE Hold Time
5
5
6
7
8
ns 14
tOED
OE to Data Delay Time
5
5
6
7
8
ns 14
tRWC
Read-Modify-Write Cycle Time
100
105
110
115
130
ns
tRRW
Read-Modify-Write Cycle
RAS Pulse Width
65
70
75
80
87
ns
tCWD
tRWD
CAS to WE Delay
RAS to WE Delay in Read-
Modify-Write Cycle
26
28
30
32
34
ns 12
50
54
58
62
68
ns 12
tCRW
tAWD
tPC
CAS Pulse Width (RMW)
Col. Address to WE Delay
Fast Page Mode Read
or Write Cycle Time
44
46
48
50
52
ns
32
35
38
41
42
ns 12
19
21
23
25
28
ns
tCP
CAS Precharge Time
tCAR
Column Address to RAS
Setup Time
3
4
5
6
7
ns
16
18
20
22
24
ns
tCAP
Access Time from Column
Precharge
19
21
23
25
27 ns 7
tDHR
Data in Hold Time Referenced
26
28
30
35
40
ns
to RAS
tCSR
CAS Setup Time CAS- before-RAS 10
10
10
10
10
ns
Refresh
tRPC
RAS to CAS Precharge Time
0
0
0
0
0
ns
tCHR
CAS Hold Time CAS-before-
7
8
8
10
12
ns
RAS Refresh
tPCM
Fast Page Mode Read-Modify-Write 56
58
60
65
70
ns
Cycle Time
tT
Transition Time (Rise and Fall)
tREF
Refresh Interval (256 Cycles)
1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 ns 15
4
4
4
4
4 ms 17
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
V53C1664H Rev. 1.0 February 1998
6