V826664G24S Datasheet, PDF (5/14 Pages) Mosel Vitelic, Corp – 512 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 64M x 64

MOSEL VITELIC
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
V826664G24S
C0 (PC2700 @ CL2.5)
Function Supported
Hex value
Byte #
Function described
A1 B0 B1 C0 A1 B0 B1 C0
0 Defines # of Bytes written into serial memory at module manufactur-
128bytes
80h
er
1 Total # of Bytes of SPD memory device
256bytes
08h
2 Fundamental memory type
SDRAM DDR
07h
3 # of row address on this assembly
13
0Dh
4 # of column address on this assembly
10
0Ah
5 # of module Rows on this assembly
2 Bank
02h
6 Data width of this assembly
64 bits
40h
7 .........Data width of this assembly
-
00h
8 VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9 DDR SDRAM cycle time at CAS Latency =2.5
8ns 7.5ns 7ns 6ns 80h 75h 70h 60h
10 DDR SDRAM Access time from clock at CL=2.5
±0.8ns ±0.75ns ±0.75ns ±0.70ns 80h 75h 75h 70h
11 DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00h
12 Refresh rate & type
7.8us & Self refresh
82h
13 Primary DDR SDRAM width
x8
08h
14 Error checking DDR SDRAM data width
N/A
00h
15 Minimum clock delay for back-to-back random column
t_CCD=1CLK
01h
address
16 DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17 DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18 DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19 DDR SDRAM device attributes : CS Latency
0CLK
01h
20 DDR SDRAM device attributes : WE Latency
1CLK
02h
21 DDR SDRAM module attributes
Differential clock /
20h
non Registered
22 DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23 DDR SDRAM cycle time at CL =2
10ns 10ns 7.5ns 7.5ns A0h A0h 75h 75h
24 DDR SDRAM Access time from clock at CL =2
±0.8ns ±0.75ns ±0.75ns ±0.70ns 80h 75h 75h 70h
25 DDR SDRAM cycle time at CL =1.5
-
-
-
-
00h
26 DDR SDRAM Access time from clock at CL =1.5
-
-
-
-
00h
27 Minimum row precharge time (=t_RP)
28 Minimum row activate to row active delay(=t_RRD)
20ns 20ns 20ns 18ns 50h 50h 50h 48h
15ns 15ns 15ns 12ns 3Ch 3Ch 3Ch 30h
V826664G24S Rev. 1.0 August 2002
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