V436516S04VTG-10PC Datasheet, PDF (5/11 Pages) Mosel Vitelic, Corp – 3.3 VOLT 16M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE

MOSEL VITELIC
SPD-Table: (Continued)
Byte
Number
30
31
32
33
34
35
36-61
62
63
64-125
126
127
128+
Function Described
Minimum RAS Pulse Width t_RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers’s Information (Optional)
Max. Frequency Specification
100 MHz Support Details
Unused Storage Location
DC Characteristics
T_A = 0°C to 70°C; V_SS = 0 V; V_DD, V_DDQ = 3.3V ± 0.3V
Symbol Parameter
V_IH
Input High Voltage
V_IL
Input Low Voltage
V_OH
Output High Voltage (I_OUT = –2.0 mA)
V_OL
Output Low Voltage (I_OUT = 2.0 mA)
I_I(L)
Input Leakage Current, any input
(0 V < V_IN < 3.6 V, all other inputs = 0V)
I_O(L)
Output leakage current
(DQ is disabled, 0V < V_OUT < V_CC)
V436516S04VTG-10PC
SPD Entry Value
45 ns
128 MByte
2 ns
1 ns
2 ns
1 ns
Revision 1.2
100 MHz
Hex Value
100 MHz
-10PC
2D
20
20
10
20
10
00
12
FD
XX
64
AF
00
Limit Values
Min.
Max.
2.0
–0.5
V_CC+0.3
0.8
2.4
—
—
0.4
–40
40
–40
40
Unit
V
V
V
V
µA
µA
V436516S04VTG-10PC Rev. 1.1 June 2000
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