V61C51161024 Datasheet, PDF (2/10 Pages) Mosel Vitelic, Corp – 64K x 16 HIGH SPEED STATIC RAM

MOSEL VITELIC
Pin Descriptions
A₀–A₁₅
Address Inputs
These 16 address inputs select one of the 64K x 16
bit segments in the RAM.
CE
Chip Enable Input
CE is active LOW. It must be active to read from or
write to the device. If chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The output enable input is active LOW. When OE
is Low with CE Low and WE High, data will be pre-
sented on the I/O pins. The I/O pins will be in the
high impedance state when OE is High.
V61C51161024
UBE, LEB Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O₀–I/O₁₅ Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
V_CC
GND
Power Supply
Ground
A₄
A₃
A₂
A₁
A₀
CE
I/O₀
I/O₁
I/O₂
I/O₃
V_CC
GND
I/O₄
I/O₅
I/O₆
I/O₇
WE
A₁₅
A₁₄
A₁₃
A₁₂
NC
44-Pin SOJ
Pin Configurations (Top View)
44-Pin TSOP-II (Standard)
1
44
A₅
2
43
A₆
3
42
A₇
4
41
OE
5
40
UBE
6
39
LBE
7
38
I/O₁₅
8
37
I/O₁₄
9
36
I/O₁₃
10
35
I/O₁₂
11
34 GND
12
33
V_CC
13
32
I/O₁₁
14
31
I/O₁₀
15
30
I/O₉
16
29
I/O₈
17
28 NC
18
27
A₈
19
26
A₉
20
25
A₁₀
21
24
A₁₁
22
23 NC
6151161024-02
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
VCC
11
GND
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A15
18
A14
19
A13
20
A12
21
NC
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6151161024-03
A5
A6
A7
OE
UBE
LBE
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
V61C51161024 Rev. 1.0 July 1998
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