MSU2051 Datasheet, PDF (12/21 Pages) Mosel Vitelic, Corp – low working voltage 16 MHz ROM less MCU

MOSEL VITELIC
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
Vdd-0.5V
70%Vdd
T CLCL
MSU2051/U2031
0.45V
20%Vdd-0.1V
T CHCL
T CLCX
Tm.I External Program Memory Read Cycle
#PSEN
T PLPH
T CLCH
T CHCX
ALE
PORT 0
PORT 2
T LHLL
T AVLL
T LLPL
T LLIV
T LLAX
T PLAZ
A0 - A7
T PLIV
T AVIV
A8 - A15
T PXIZ
T PXIX
Instruction. IN
A0 - A7
A8 - A15
Tm.II External Data Memory Read Cycle
#PSEN
ALE
#RD
PORT 0
PORT 2
T LLDV
T LLYL
T RLRH
T AVLL
T LLAX
A0-A7
from Ri or
T AVYL
T AVDV
T RLDV
T RLAZ
P2.0-P2.7 or A8-A15 from DPH
T YHLH
T RHDZ
T RHDX
DATA IN
A0-A7
From
INSTR.
IN
A8-A15 from PCH
Rev. 1.0 February 1998
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