V62C3162048L Datasheet, PDF (11/13 Pages) Mosel Vitelic, Corp – Ultra Low Power 128K x 16 CMOS SRAM

V62C3162048L(L)
Data Retention Characteristics (L Version Only)⁽¹⁾
Parameter
V_CC for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time⁽²⁾
Symbol
V_DR
I_CCDR
t_CDR
t_R
Test Condition
CE > V_CC - 0.2V
V_IN > V_CC - 0.2V or
V_IN < 0.2V
Min
2.0
-
0
t_RC
Max
-
1
-
-
Unit
V
µA
ns
ns
Data Retention Waveform (L Version Only) (T_A = 0⁰C to +70⁰C / -40⁰C to +85⁰C)
V_CC
CE
Vcc_typ
t_CDR
V_IH
Data Retention Mode
V_DR > 2.0V
V_DR
Vcc_typ
t_R
V_IH
Notes (Write Cycle)
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is High for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
11
REV. 1.2 May 2001 V62C3162048L(L)