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V29C51000T Datasheet, PDF (10/16 Pages) Mosel Vitelic, Corp – 512K BIT 65,536 x 8 BIT 5 VOLT CMOS FLASH MEMORY
MOSEL VITELIC
V29C51000T/V29C51000B
Table 2. Command Codes
Command
Sequence
First Bus
Second Bus
Third Bus
Fourth Bus
Program Cycle Program Cycle Program Cycle Program Cycle
Address Data Address Data Address Data Address Data
Fifth Bus
Six Bus
Program Cycle Program Cycle
Address Data Address Data
Read
XXXXH F0H
Read
5555H AAH 2AAAH 55H 5555H F0H RA
RD
Autoselect
5555H
AAH 2AAAH 55H 5555H
90H 00H
01H
40H
00H(1)
A0H(2)
Byte
Program
5555H AAH 2AAAH 55H 5555H A0H PA
PD(4)
Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H PA(3)
30H
NOTES:
1. Top Boot Sector
2. Bottom Boot Sector
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
the device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit.
The V29C51000T/V29C51000B is shipped with
pre-erased sectors (all bits = 1).
attempt to read the device will received the
complement of the loaded data on I/O7. Once the
program cycle is completed, I/O7 will show true
data, and the device is then ready for the next
cycle.
Chip Erase Cycle
The V29C51000T/V29C51000B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The chip erase operation is performed
sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Program Cycle Status Detection
There are two methods for determining the state
of the V29C51000T/V29C51000B during a
program (erase/program) cycle: DATA Polling
(I/O7) and Toggle Bit (I/O6).
DATA Polling (I/O7)
The V29C51000T/V29C51000B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
Toggle Bit (I/O6)
The V29C51000T/V29C51000B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O6 toggling between 1 and 0. Once the program is
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
Boot Block Protection
The V29C51000T/V29C51000B features
hardware Boot Block Protection. This feature will
prevent erasing/programming of data in the Boot
Block once the feature is enabled (see Table 3).
The device is shipped with the Boot Block
unprotected.
Autoselect
The V29C51000T/V29C51000B features an
Autoselect mode to identify the Boot Block
(protected/unprotected), the Device (Top/Bottom),
and the manufacturer ID.
To get to the Autoselect mode, a high voltage
(VH) must be applied to the A9 pin. Once the A9
signal is returned to LOW or HIGH, the device will
return to the previous mode.
V29C51000T/V29C51000B Rev. 0.5 October 2000
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