V62C518256 Datasheet, PDF (1/12 Pages) Mosel Vitelic, Corp – 32K X 8 STATIC RAM

MOSEL VITELIC V62C518256
32K X 8 STATIC RAM
PRELIMINARY
Features
s High-speed: 35, 70 ns
s Ultra low DC operating current of 5mA (max.)
s Low Power Dissipation:
– TTL Standby: 3 mA (Max.)
– CMOS Standby: 20 µA (Max.)
s Fully static operation
s All inputs and outputs directly compatible
s Three state outputs
s Ultra low data retention current (V_CC = 2V)
s Single 5V ± 10% Power Supply
s Packages
– 28-pin TSOP (Standard)
– 28-pin 600 mil PDIP
– 28-pin 330 mil SOP (450 mil pin-to-pin)
Description
The V62C518256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC’s high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Functional Block Diagram
A₀
V_CC
Row
Decoder
512 x 512
Memory Array
GND
A₈
I/O₀
Column I/O
Input
Data
Circuit
Column Decoder
I/O₇
A₉
A₁₄
CE
OE
WE
Control
Circuit
518256-01
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
–40°C to +85°C
Package Outline
T
P
F
•
•
•
•
•
•
Access Time (ns)
35
70
•
•
•
•
Power
L
LL
•
•
•
•
Temperature
Mark
Blank
I
V62C518256 Rev. 2.3 November 1998
1