V62C2162048L Datasheet, PDF (1/13 Pages) Mosel Vitelic, Corp – Ultra Low Power 128K x 16 CMOS SRAM

Features
• Low-power consumption
- Active: 65mA I_CC at 35ns
- Stand-by: 10 µA (CMOS input/output)
2 µA (CMOS input/output, L version)
• 35/45/55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.2V to 2.7V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOP II / 48-fpBGA
V62C2162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Functional Description
The V62C2162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
TSOPII / 48-fpBGA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Vcc
Vss
Memory Array
1024 X 2048
Data
Cont
I/O Circuit
Data
Cont
Column Select
A10 A11 A12 A13 A14 A15 A16
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O1
7
I/O2
8
I/O3
9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A16 18
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 ^I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
1
REV. 1.3 OCT 2001 V62C2162048L(L)