V62C1801024L Datasheet, PDF (1/10 Pages) Mosel Vitelic, Corp – Ultra Low Power 128K x 8 CMOS SRAM

V62C1801024L(L)
Ultra Low Power
128K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 20mA at 70ns
- Stand-by: 5 µA (CMOS input/output)
1 µA CMOS input/output, L version
• Single +1.8V to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1 , CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
Functional Description
The V62C1801024L is a low power CMOS Static RAM or-
ganized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW CE1 , an active HIGH CE2, an
active LOW OE, and Tri-state I/O’s. This device has an a-
utomatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1 ) with Write Enable (WE) LOW, and Chip Ena-
ble 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance st-
ate when the device is deselected: the outputs are disabled
during a write cycle.
The V62C1801024LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1801024L is available in
a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP (See next page)
INPUT BUFFFEERR
A0
AA^A21¹
A^A3²
AA43
1¹0⁰2²4⁴
A_A5₄
A_A6₅
10X^X24
A_A7₆
1024
A8
AA97
A8
COLUMN DECODER
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16
A9 A10 A11 A12 A13 A14 A15 A16
I_I/_/OO8₇
I/O1
I/O0
OE
CONTROL WE
C^CO^IRN^CT^UR^IO^TL
O_CE_E1
W_CEE₂
CIRCUIT ^CE1
CE2
A11
1
A9
2
A8
3
A13
4
WE
5
CE2
6
A15
7
Vcc
8
NC
9
A16
10
A14
11
A12
12
A7
13
A6
14
A5
15
A4
16
1
REV. 1.1 April 2001 V62C1801024L(L)
32
OE
31
A10
30
CE1
29
I/O8
28
I/O7
27
I/O6
26
I/O5
25
I/O4
24
GND
23
I/O3
22
I/O2
21
I/O1
20
A0
19
A1
18
A2
17
A3