V61C518256 Datasheet, PDF (1/12 Pages) Mosel Vitelic, Corp – 32K X 8 HIGH SPEED STATIC RAM

MOSEL VITELIC
V61C518256
32K X 8 HIGH SPEED
STATIC RAM
PRELIMINARY
Features
s High-speed: 10, 12, 15 ns
s Low Power Dissipation:
– CMOS Standby: 0.5 mA (Max.)
s Fully static operation
s All inputs and outputs directly compatible
s Three state outputs
s Ultra low data retention current (V_CC = 2V)
s Single 5V ± 10% Power Supply
s Packages
– 28-pin TSOP (Standard)
– 28-pin 300 mil SOJ
Description
The V61C518256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC’s high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Functional Block Diagram
A₀
A₁
V_CC
GND
A₆
Row
Decoder
512 x 512
Memory Array
A₁₀
A₁₃
A₁₄
I/O₀
Column I/O
Input
Data
Circuit
Column Decoder
I/O₇
A₂
A₅ A₁₁ A₁₂
CE
OE
WE
Control
Circuit
518256-01
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
T
N
R
•
•
•
Access Time (ns)
10
12
15
•
•
•
V61C518256 Rev. 0.3 July 1998
1
Temperature
Mark
Blank