V61C5181024 Datasheet, PDF (1/12 Pages) Mosel Vitelic, Corp – 128K X 8 HIGH SPEED STATIC RAM

MOSEL VITELIC
V61C5181024
128K X 8 HIGH SPEED
STATIC RAM
PRELIMINARY
Features
s High-speed: 10, 12, 15 ns
s Fully static operation
s All inputs and outputs directly TTL compatible
s Three state outputs
s Low data retention current (V_CC = 2V)
s Single 5V ± 10% Power Supply
s Low CMOS Standby current of 5 mA max
s Packages
– 32-pin TSOP
– 32-pin 300 mil SOJ
Description
The V61C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing
with common system bus structures. The
V61C5181024 is available in 32-pin SOJ, PDIP and
TSOP.
Functional Block Diagram
A₀
V_CC
Row
Decoder
Memory Array
GND
A₈
I/O₀
Column I/O
Input
Data
Circuit
Column Decoder
I/O₇
A₉
CE1
CE2
Control
OE
Circuit
WE
A₁₆
5181024 01
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
R
•
•
V61C5181024 Rev. 1.1 July 1998
Access Time (ns)
10
12
15
•
•
•
1
Temperature
Mark
Blank