V55C2128164V Datasheet, PDF (1/44 Pages) Mosel Vitelic, Corp – 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16

MOSEL VITELIC
V55C2128164V(T/B)
128Mbit LOW-POWER SDRAM
2.5 VOLT, TSOP II / BGA PACKAGE
8M X 16
PRELIMINARY
System Frequency (f_CK)
Clock Cycle Time (t_CK3)
Clock Access Time (t_AC3) CAS Latency = 3
Clock Access Time (t_AC2) CAS Latency = 2
Clock Access Time (t_AC1) CAS Latency = 1
6
166 MHz
6 ns
5.4 ns
5.4 ns
19 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
19 ns
7
143 MHz
7 ns
5.4 ns
6 ns
19 ns
8PC
125 MHz
8 ns
6 ns
6 ns
19 ns
10
100MHz
10 ns
7 ns
8 ns
22 ns
Features
■ 4 banks x 2Mbit x 16 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency:1, 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode and Clock Suspend Mode
■ Deep Power Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 9x8 mm and 54 pin
TSOP II
■ VDD=2.5V, VDDQ=1.8V
■
■ Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■ Operating Temperature Range
Commercial (0°C to 70°C)
Extended (-25°C to +85°C)
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-25°C to 85°C
Package Outline
T/B
6
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V55C2128164V(T/B) Rev. 1.2 August 2002
1
Access Time (ns)
7PC
7
8PC
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Temperature
10
Mark
•
Commercial
•
Extended