V54C333322V Datasheet, PDF (1/21 Pages) Mosel Vitelic, Corp – 200/183/166 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 1M X 32 SDRAM 2 BANKS X 512Kbit X 32

MOSEL VITELIC
V54C333322V
200/183/166 MHz 3.3 VOLT
ULTRA HIGH PERFORMANCE
1M X 32 SDRAM 2 BANKS X 512Kbit X 32
PRELIMINARY
V54C333322V
Clock Frequency (t_CK)
CAS Latency
Cycle Time (t_CK)
Access Time (t_AC)
-5
-55
-6
Unit
200
183
166
MHz
3
3
3
clocks
5
5.5
6
ns
5
5.5
6
ns
Features
s JEDEC Standard 3.3V Power Supply
s The V54C333322V is ideally suited for high
performance graphics peripheral applications
s Single Pulsed RAS Interface
s Programmable CAS Latency: 2, 3
s All Inputs are sampled at the positive going edge
of clock
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
s DQM 0-3 for Byte Masking
s Auto & Self Refresh
s 2K Refresh Cycles/32 ms
s Burst Read with Single Write Operation
Description
The V54C333322V is a 33,554,432 bits synchro-
nous high data rate DRAM organized as 2 x
524,288 words by 32 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.
V54C333322V Rev. 2.0 May 2000
1