V53C832L Datasheet, PDF (1/18 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 3.3 VOLT 256K X 32 EDO PAGE MODE CMOS DYNAMIC RAM

MOSEL VITELIC
V53C832L
HIGH PERFORMANCE
3.3 VOLT 256K X 32 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t_RAC)
Max. Column Address Access Time, (t_CAA)
Min. Extended Data Out Page Mode Cycle Time, (t_PC)
Min. Read/Write Cycle Time, (t_RC)
30
30 ns
16 ns
12 ns
65 ns
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
Features
s 256K x 32-bit organization
s EDO Page Mode for a sustained data rate of
83 MHz
s RAS access time: 30, 35, 40 ns
s Four CAS Inputs for Byte Read and Byte Write
Control
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8 ms
s Available in 100-pin PQFP and 100-pin LQFP
packages
s Single +3.3V ± 0.3V Power Supply
s TTL Interface
Description
The V53C832L is a high speed 262,144 x 32 bit
high performance CMOS dynamic random access
memory. The V53C832L offers a combination of
unique features including: EDO Page Mode opera-
tion for higher sustained bandwidth with Page Mode
cycle times as short as 12ns. All inputs are TTL
compatible. Input and output capacitance is signifi-
cantly lowered to increase performance and mini-
mize loading. These features make the V53C832L
ideally suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
Q
TQ
•
•
Access Time (ns)
30
35
40
•
•
•
Power
Std.
•
Temperature
Mark
Blank
V53C832L Rev. 1.6 August 1999
1