V53C8126H Datasheet, PDF (1/18 Pages) Mosel Vitelic, Corp – ULTRA-HIGH PERFORMANCE, 128K X 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM

MOSEL VITELIC
V53C8126H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (t_RAC)
Max. Column Address Access Time, (t_CAA)
Min. Fast Page Mode Cycle Time, (t_PC)
Min. Read/Write Cycle Time, (t_RC)
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
PREVL5I3MCI8N1A2R6YH
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
Features
s 128K x 8-bit organization
s RAS access time: 35, 40, 45, 50 ns
s Fast Page Mode supports sustained I/O data
rates up to 40 MHz
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval
• V53C8126H – 512 cycles/8 ms
s Available in 26/24 pin 300 mil SOJ and 28 pin
TSOP package
Description
The V53C8126H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8126H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 256
columns (x8) bits within a row with cycle times as
short as 21 ns. Because of static circuitry, the CAS
clock is not in the critical timing path. The flow-
through column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8126H ideally suited for graphics,
digital signal processing and high performance
peripherals.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
K
T
•
•
Access Time (ns)
35
40
45
50
•
•
•
•
Power
Std.
•
V53C8126H Rev. 1.1 July 1997
1
Temperature
Mark
Blank