V53C316405A Datasheet, PDF (1/24 Pages) Mosel Vitelic, Corp – 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM

MOSEL VITELIC
V53C316405A
3.3 VOLT 4M x 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C316405A
Max. RAS Access Time, (t_RAC)
Max. Column Address Access Time, (t_CAA)
Min. Extended Data Out Page Mode Cycle Time, (t_PC)
Min. Read/Write Cycle Time, (t_RC)
50
50 ns
25 ns
20 ns
84 ns
60
60 ns
30 ns
25 ns
104 ns
Features
s 4M x 4-bit organization
s EDO Page Mode for a sustained data rate
of 50 MHz
s RAS access time: 50, 60 ns
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh and Hidden Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
s Single +3.3V ±0.3V Power Supply
s TTL Interface
Description
The V53C316405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access mem-
ory. The V53C316405A offers Page mode opera-
tion with Extended Data Output. The V53C316405A
has asymmetric address, 12-bit row and 10-bit col-
umn.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C316405A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
K
T
•
•
V53C316405A Rev. 1.2 March 1998
Access Time (ns)
50
60
•
•
1
Power
Std.
•
Temperature
Mark
Blank