V53C16256H Datasheet, PDF (1/19 Pages) Mosel Vitelic, Corp – 256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM

MOSEL VITELIC
V53C16256H
256K x 16 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t_RAC)
Max. Column Address Access Time, (t_CAA)
Min. Fast Page Mode Cycle Time, (t_PC)
Min. Read/Write Cycle Time, (t_RC)
30
30 ns
16 ns
19 ns
65 ns
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
60
60 ns
30 ns
35 ns
110 ns
Features
s 256K x 16-bit organization
s Fast Page Mode for a sustained data rate
of 53 MHz.
s RAS access time: 30, 35, 40, 45, 50, 60 ns
s Dual CAS Inputs
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8 ms
s Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
s Single +5V ±10% Power Supply
s TTL Interface
Description
The V53C16256H is a 262,144 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C16256H offers Fast Page mode with
dual CAS inputs. An address, CAS and RAS input
capacitances are reduced to one quarter when the
x4 DRAM is used to construct the same memory
density. The V53C16256H has symmetric address
and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 19ns.
The V53C16256H is best suited for graphics, and
DSP applications.
Device Usage Chart
Operating
Package Outline
Temperature
Range
K
T
30
0°C to 70 °C
•
•
•
-40°C to +85°C
•
•
•
Access Time (ns)
35
40
45
50
•
•
•
•
•
•
•
•
Power
Temperature
60
Std.
Mark
•
•
Blank
•
•
I
V53C16256H Rev. 2.3 June 1998
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