V53C16129H Datasheet, PDF (1/20 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 128K X 16 BIT FAST PAGE MODE CMOS DYNAMIC RAM

MOSEL VITELIC
V53C16129H
HIGH PERFORMANCE
128K x 16 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t_RAC)
Max. Column Address Access Time, (t_CAA)
Min. Fast Page Mode Cycle Time, (t_PC)
Min. Read/Write Cycle Time, (t_RC)
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
60
60 ns
30 ns
27 ns
110 ns
Features
s 128K x 16-bit organization
s EDO Page Mode for a sustained data rate
of 67 MHz
s RAS access time: 40, 45, 50, 60 ns
s Dual CAS Inputs
s Low Power Dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8ms
s Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s Single +5V ± 10% Power Supply
s TTL Interface
Description
The V53C16129H is a 131,072 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C16129H offers Page mode with
Extended Data Output. EDO Page Mode operation
allows random access up to 512 x 16 bits, within a
page, with cycle times as short as 15 ns. An
address, CAS and RAS input capacitances are
reduced to minimize the loading. The V53C16129H
has asymmetric address 8-bit row and 9-bit
column.
All inputs are TTL compatible. The V53C16129H
is best suited for graphics, and DSP applications
requiring high performance memories.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
K
T
•
•
Access Time (ns)
40 45 50 60
•
•
•
•
Power
Std.
•
Temperature
Mark
Blank
V53C16129H Rev. 1.2 July 1997
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