MSM8512C-020 Datasheet, PDF (1/11 Pages) MOSAIC – 512K x 8 Static RAM Issue 5.2 April 2001

MSM8512C - 020
Issue 5.2 April 2001
Description
Block Diagram
The MSM8512C is a 512K x 8 SRAM monolithic
device available in Chip Size BGA (Ball Grid Array)
package, with access times of 20ns. The device is
available to commercial and industrial temperature
grades.
/CS
/OE
/WE
The Chip Size BGA provides an ultra high density
memory packaging solution.
A0
D0
A1
D1
The Chip Size BGA occupies less than 50% of the _A2
D2
board area of conventional SOP, SOJ and TSOP II A3
512K x 8
D3
packages.
A4
D4
A5
SRAM
D5
A6
D6
A7
D7
A8
Features
• Access times of 20 ns.
• 5V + 10%, (3.3V Under Development)
• Commercial & Industrial temperature grades
• Chip Size BGA.
• 48 pad, 1mm pad pitch, package.
• Eutectic 63/67 solder ball attach.
• Low Power Dissipation.
Operating
1 W (max)
Standby (CMOS) 66mW (max)
• Completely Static Operation.
• 4 layer BT substrate with power and ground
planes.
• Pinout and footprint will remain the same in the
event of a die shrink.
Package Details
48D - 48 Ball, 1mm pitch Chip Size BGA
Max. Dimensions (mm) - 8.00 x 10.00 x 1.40
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A18
D0~D7
/CS
/WE
/OE
NC
V_CC
GND