MS6260_1 Datasheet, PDF (6/14 Pages) MOSA ELECTRONICS – Gain and Attenuation Volume Controller IC One Set of Stereo Input, Low voltage Gain and Attenuation 15~-79dB, Good PSRR

MOSA
MS6260
Gain And Attenuation Volume Controller IC
Acknowledge
During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral
(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that
the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.
SCL
1
2
3
7
8
9
SDA
Start
MSB
Acknowledge
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,
the SDA line will remain at the HIGH level during the ninth (9^th) clock pulse. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
Timing of SDA and SCL bus lines
SDA
tf
tLOW
tr
tSU;DAT
tf
SCL
tHD;STA
tSP tr
tBUF
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
PS
Standard mode
Symbol
Parameter
Min Max Unit
f_SCL
t_HD:STA
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
0
100
kHz
4.0
-
us
t_LOW
LOW period of the SCL clock
4.7
-
us
t_HIGH HIGH period of the SCL clock
4.0
-
us
t_SU:STA
t_HD:DAT
Set-up time for a repeated START condition
Data hold time:
For I²C-bus devices
4.7
-
us
0
3.45
us
t_SU:DAT Data-set-up time
250
-
ns
t_r
Rise time of both SDA and SCL signals
-
1000
ns
t_f
Fall time of both SDA and SCL signals
-
300
ns
t_SU:STO Set-up time for STOP condition
4.0
-
us
t_BUF
Bus free time between a STOP and START condition
4.7
-
us
C_b
Capacitive load for each bus line
-
400
pF
V_nL
Noise margin at the LOW level for each connected device (including
hysteresis)
0.1V_DD
-
V
V_nH
Noise margin at the HIGH level for each connected device (including
hysteresis)
0.2V_DD
-
V
REV 3
6
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