URA2405LD-20WR2 Datasheet, PDF (9/10 Pages) MORNSUN Science& Technology Ltd. – REGULATED SINGLE/DUAL OUTPUT DC-DC CONVERTER

PACKAGE DIAGRAM
Special Package Series（A2S/A4S）
TEST CONFIGURATIONS
Input Reflected-Ripple Current Test Setup
Input reflected-ripple current is measured with an inductor Lin and Capacitor Cin to simulate source impedance.
Oscilloscope
Lin
DC DC ^Current
Cin Probe
Load
Lin(4.7µH) Cin(220µF, ESR < 1.0Ω at 100 KHz)
TRIM APPLICATION & TRIM RESISTANCE
Application circuit for TRIM (Part in broken line is the interior of models)
+ Vo
+Vo
R1
R3
Vref
R2
RT
Trim
R1
Vref ^R3
R2
RT
Trim
Formula for resistance of Trim
up: RT=
aR2
R2-a
- R3
aR1
down: RT= _R1-a -R3
a=
Vr e f
Vo’-Vref
R1
Vo ’- Vr e f
a=
R2
Vr e f
0V
0V
Trim up
Trim down
Note: Leave open if not used; Value for R1, R2, R3, and V_ref refer to the above table 1; R_T: Resistance of Trim; a: User-defined parameter, no actual meanings.; Vo’: The
trim up/down voltage.
Vo
Parameter
R1(KΩ)
R2(KΩ)
R3(KΩ)
Vref(V)
3.3(VDC)
4.801
2.863
15
1.24
(Table 1)
5(VDC) 9(VDC)
2.883
2.864
10
2.5
7.5
2.864
15
2.5
12(VDC)
10.971
2.864
17.8
2.5
15(VDC)
14.497
2.864
17.8
2.5
24(VDC)
24.872
2.863
20
2.5
DESIGN CONSIDERATIONS
①Recommended circuit
All the URA_LD-20WR2 & URB_LD-20WR2 Series have been tested according to the following recommended testing circuit before leaving
factory (see Figure 4).
If you want to further decrease the input/output ripple, you can increase a capacitance properly or choose capacitors with low ESR, but the
greatest capacitance of its filter capacitor must less than the Max. Capacitive Load. The recommended capacitance of its filter capacitor sees
(Table 2).
The copyright and authority for the interpretation of the products are reserved by MORNSUN
URA_LD-20WR2 & URB_LD-20WR2
2013.11.29-A/3
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