DS90C387A_11 Datasheet, PDF (17/21 Pages) Texas Instruments – Dual Pixel LVDS Display Interface / FPD-Link

Applications Information (Continued)
DS90C387/DS90CF388
The DS90C387A/CF388A chipset is electrically similar to the
DS90C387/CF388. The DS90C387/CF388 is intended for
improved support of longer cable drive. Cable drive is en-
hanced with a user selectable pre-emphasis feature that
provides additional output current during transitions to coun-
teract cable loading effects. Optional DC balancing on a
Configuration Table
cycle-to-cycle basis, is also provided to reduce ISI (Inter-
Symbol Interference). With pre-emphasis and DC balancing,
a low distortion eye-pattern is provided at the receiver end of
the cable. A cable deskew capability has been added to
deskew long cables of pair-to-pair skew of up to +/−1 LVDS
data bit time (up to 80 MHz Clock Rate). These three en-
hancements allow cables 5+ meters in length to be driven
depending upon media and clock rate.
Pin
R_FB (Tx only)
R_FDE (both Tx and Rx)
DUAL (Tx only)
TABLE 3. Transmitter / Receiver configuration table
Condition
R_FB = V_CC
R_FB = GND
R_FDE = V_CC
R_FDE = GND
DUAL=V_CC
DUAL=1/2V_CC
DUAL=Gnd
Configuration
Rising Edge Data Strobe
Falling Edge Data Strobe
Active data DE = High
Active data DE = Low
48-bit color (dual pixel) support
Single-to-dual support
24-bit color (single pixel) support
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