M37641M8 Datasheet, PDF (85/149 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINARY _{NSocothimcaene:gpTeah.riasmisetnrioct} ^{laimfiintsalasrepescuibfijceacttioton.}
MITSUBISHI MICROCOMPUTERS
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Requirements
In Vcc = 5 V
Table 14 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ. Max.
tW(RESET)
Reset input “L” pulse width
2
µs
tC(XIN)
Main clock input cycle time (Note)
41.66
ns
tWH(XIN)
Main clock input “H” pulse width
0.4•tc(XIN)
ns
tWL(XIN)
Main clock input “L” pulse width
0.4•tc(XIN)
ns
tC(XCIN)
Sub-clock input cycle time
200
ns
tWH(XCIN)
Sub-clock input “H” pulse width
0.4•tc(XCIN)
ns
tWL(XCIN)
Sub-clock input “L” pulse width
0.4•tc(XCIN)
ns
tC(INT)
INT0, INT1 input cycle time
200
ns
tWH(INT)
INT0, INT1 input “H” pulse width
90
ns
tWL(INT)
INT0, INT1 input “L” pulse width
90
ns
tC(CNTRI)
CNTR0, CNTR1 input cycle time
200
ns
tWH(CNTRI)
CNTR0, CNTR1 input “H” pulse width
80
ns
tWL(CNTRI)
CNTR0, CNTR1 input “L” pulse width
80
ns
td(φ -TOUT)
Timer TOUT delay time
15
ns
td(φ -CNTR0)
Timer CNTR0 delay time (Pulse output mode)
15
ns
tC(CNTRE0)
Timer CNTR0 input cycle time (Event counter mode)
200
ns
tWH(CNTRE0)
Timer CNTR0 input “H” pulse width (Event counter mode)
0.4•tc(CNTRE0)
ns
tWL(CNTRE0)
Timer CNTR0 input “L” pulse width (Event counter mode)
0.4•tc(CNTRE0)
ns
td(φ -CNTR1)
Timer CNTR1 delay time (Pulse output mode)
15
ns
tC(CNTRE1)
Timer CNTR1 input cycle time (Event counter mode)
200
ns
tWH(CNTRE1)
Timer CNTR1 input “H” pulse width (Event counter mode)
0.4•tc(CNTRE1)
ns
tWL(CNTRE1)
Timer CNTR1 input “L” pulse width (Event counter mode)
0.4•tc(CNTRE1)
ns
tC(SCLKE)
Serial I/O external clock input cycle time
400
ns
tWH(SCLKE)
Serial I/O external clock input “H” pulse width
190
ns
tWL(SCLKE)
Serial I/O external clock input “L” pulse width
180
ns
tsu(SRXD-SCLKE) Serial I/O input setup time (external clock)
15
ns
th(SCLKE-SRXD) Serial I/O input hold time (external clock)
10
ns
td(SCLKE-STXD) Serial I/O output delay time (external clock)
25
ns
tv(SCLKE-SRDY) Serial I/O SRDY valid time (external clock)
26
ns
tc(SCLKI)
Serial I/O internal clock output cycle time
166.66
ns
tWH(SCLKI)
Serial I/O internal clock output “H” pulse width
0.5•tc(SCLKI) – 5
ns
tWL(SCLKI)
Serial I/O internal clock output “L” pulse width
0.5•tc(SCLKI) – 5
ns
tsu(SRXD-SCLKI) Serial I/O input setup time (internal clock)
20
ns
th(SCLKI-SRXD) Serial I/O input hold time (internal clock)
5
ns
td(SCLKI-STXD) Serial I/O output delay time (internal clock)
5
ns
Note: Make sure not to exceed 12 MHz of φ, in other words, tc(φ) ≥ 83.33 ns). For example, set bit 7 of the clock control register (CCR) to “0” in the case of
tc(XIN) < 41.66 ns.
85