M38867M8A Datasheet, PDF (76/110 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Functional Outline (serial I/O mode)
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is fol-
lowed by address input and data input/output according to the
contents of the command. Table 26 shows the software com-
mands used in the serial I/O mode. The following explains each
software command.
Table 26 Software command (serial I/O mode)
Number of transfers First command
Command
code input
Second
Read
0016
Read address L (Input)
Program
4016
Program address L (Input)
Program verify
C016
Verify data (Output)
Erase
2016
2016 (Input)
Erase verify
A016
Verify address L (Input)
Error check
8016
Error code (Output)
Third
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Fourth
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
q Read command
Input command code 0016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the M38869FFAHP/GP
reads out the contents of the specified address, and then latchs it
__
into the internal data latch. When the OE pin is released back high
and serial clock is input to the SCLK pin, the read data that has
been latched into the data latch is serially output from the SDA
pin.
SCLK
SDA
tCH
tCH
A0
A7
A8
A15
D0
D7
00000000
Command code input (0016) Read address input (L) Read address input (H)
Read data output
tCR
tWR
tRC
OE
BUSY “L”
Read
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 73 Timings during reading
76