M38503M4H Datasheet, PDF (6/51 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Currently planning products are listed below.
Table 2 Support products
Product name
M38503M2H-XXXSP
M38503M2H-XXXFP
M38503M4H-XXXSP
M38503M4H-XXXFP
M38504M6-XXXSP
M38504E6-XXXSP
M388504E6SP
M388504E6SS
M38504M6-XXXFP
M38504E6-XXXFP
M38504E6FP
ROM size (bytes)
ROM size for User in ( )
8192
(8062)
16384
(16254)
24576
(24446)
RAM size (bytes)
512
512
640
As of Feb. 2000
Package
Remarks
42P4B
42P2R-A/E
424P4B
42P2R-A/E
424P4B
42S1B-A
42P2R-A/E
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Table 3 3850 group (standard) and 3850 group (spec. H)
corresponding products
3850 group (standard)
3850 group (spec. H)
M38503M2-XXXFP/SP
M38503M2H-XXXFP/SP
M38503M4-XXXFP/SP
M38503M4H-XXXFP/SP
M38503E4-XXXFP/SP
M38504M6-XXXFP/SP
M38503E4FP/SP
M38504E6-XXXFP/SP
M38503E4SS
M38504E6FP/SP
M38504E6SS
M38507M8-XXXFP/SP
M38507F8FP/SP
Table 4 Differences between 3850 group (standard) and 3850 group (spec. H)
Serial I/O
3850 group (standard)
1: Serial I/O (UART or Clock-synchronized)
A-D converter
Large current port
Unserviceable in low-speed mode
5: P13–P17
3850 group (spec. H)
2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
8: P10–P17
Notes on differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group
(spec. H).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
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