MH16S72DDFA-7 Datasheet, PDF (54/56 Pages) Mitsubishi Electric Semiconductor – 1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31
Density of each bank on module
32
Command and Address signal input setup time
33
Command and Address signal input hold time
34
Data signal input setup time
35
36-61
62
63
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
73-90
Manufactures Part Number
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
-7
Intel specification CAS# Latency support
-8
Unused storage locations
128MByte
2ns
1ns
2ns
1ns
option
rev 1.2A
Check sum for -7
Check sum for -8
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH16S72DDFA-7
MH16S72DDFA-8
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0
CL=3,AP,CK0
open
20
20
10
20
10
00
12
3F
7F
1CFFFFFFFFFFFFFF
01
02
03
04
4D483136533732444446412D372020202020
4D483136533732444446412D382020202020
rrrr
yyww
ssssssss
00
64
8F
8D
00
MIT-DS-0347-0.1
MITSUBISHI
ELECTRIC
15/Oct./1999
54