M37271MF Datasheet, PDF (54/97 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap oc-
curs between the horizontal display start position set by
the horizontal position register and the most left dot of the
1st block. Accordingly, when 2 blocks have different pre-
divide ratios, their horizontal display start position will not
match.
2 : The horizontal start position is based on the OSD clock
source cycle selected for each block. Accordingly, when 2
blocks have different OSD clock source cycles, their hori-
zontal display start position will not match.
HSYNC
Note 1
Note 2
1TC
Block 1 (Pre-divide ratio = 1, clock source = data slicer clock)
4TOSC!N
1TC
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
1TC
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
4TOSC’!N
1TC
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
Fig. 60. Notes on horizontal display start position
(3) Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
The dot size of the layer 1 is specified by bits 6 to 3 of the block
control register.
The dot size of the layer 2 is specified by the following bits : bits 3
and 4 of the block control register, bit 6 of the clock source control
register. Refer to Figure 53 (the structure of the block control regis-
ter), refer to Figure 62 (the structure of the clock source control reg-
ister).
The block diagram of dot size control circuit is shown in Figure 61.
Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode.
2 : The pre-divide ratio of the OSD mode block on the layer 2
must be same as that of the CC mode block on the layer 1
by bit 6 of the clock source control register.
3 : In the bi-scan mode, the dot size in the vertical direction is
2 times as compared with the normal mode. Refer to “(13)
Scan Mode” about the scan mode.
OSC1
Data slicer clock
HSYNC
Synchronization
circuit
CS0
Cycle!2
Clock cycle
= 1TC
Cycle!3
Pre-divide circuit
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
Fig. 61. Block diagram of dot size control circuit
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