M37224M3 Datasheet, PDF (50/83 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses (2 blocks)
can be corrected, a program for correction is stored in the ROM cor-
rection memory in RAM. The ROM memory for correction is 32 bytes
! 2 blocks.
Block 1 : addresses 02C016 to 02DF16
Block 2 : addresses 02E016 to 02FF16
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the ROM correction address, the main pro-
gram branches to the correction program stored in the ROM memory
for correction. To return from the correction program to the main pro-
gram, the op code and operand of the JMP instruction (total of 3
bytes) are necessary at the end of the correction program. When the
blocks 1 and 2 are used in series, the above instruction is not needed
at the end of the block 1.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1 : Specify the first address (op code address) of each
instruction as the ROM correction address.
2 : Use the JMP instruction (total of 3 bytes) to return from
the main program to the correction program.
3 : Do not set the same ROM correction address to the blocks
1 and 2.
ROM correction address 1 (high-order) 021716
ROM correction address 1 (low-order) 021816
ROM correction address 2 (high-order) 021916
ROM correction address 2 (low-order) 021A16
Fig. 51. ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
00
ROM correction enable register (RCR) [Address 021B16]
B
Name
0 Block 1 enable bit (RC0)
1 Block 2 enable bit (RC1)
2,3 _{Fix these bits to “0.”}
Functions
0: Disabled
1: Enabled
0: Disabled
1: Enabled
4 Nothing is assigned. These bits are write disable bits. When
to these bits are read out, the values are “0.”
7
After reset R W
0 _RW
0 _RW
0 _RW
0 _R—
Fig. 52. ROM Correction Enable Register
50